// *********************************************************************************
// Project Name : zkx2024
// Author       : Jlan
// Email        : 15533610762@163.com
// Create Time  : 2024-05-15
// File Name    : .v
// Module Name  :
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-15    Macro           1.0                     Original
//  
// *********************************************************************************

module dp_sram_fix#(
    parameter integer DEPTH = 8192, // Depth of the SRAM
    parameter integer WIDTH = 36    // Width of the data bus
)(
    input wire clk,                  // Clock signal
    input wire cs,                   // Chip select signal
    input wire we,                   // Write enable signal
    input wire re,                   // readt enable signal
    //input wire oe,                   // Output enable signal
    input wire [WIDTH-1:0] data_in, // Data input bus
    input wire [$clog2(DEPTH)-1:0] rd_addr, // Address input bus
    input wire [$clog2(DEPTH)-1:0] wr_addr, // Address input bus
    output reg [WIDTH-1:0] data_out // Data output bus
);

// Memory array to simulate the storage of the SRAM
//reg [WIDTH-1:0] mem [0:DEPTH-1];
bit [WIDTH-1:0] mem [wire [$clog2(DEPTH)-1:0]];
// Write operation block
always @(posedge clk) begin
    if (cs && we) begin
        mem[wr_addr] <= data_in; // Write data to the memory array at the address 'addr'
    end
end

// Read operation block
always @(posedge clk) begin
    if (cs && re) begin
        data_out <= mem[rd_addr]; // When not in output enable mode, read data from the memory array
    end else if (!cs || !re) begin
        // When in high-Z mode (chip select high or output enable high), keep data_out in high impedance
        // 'bx represents a value that is unknown or not driven
        data_out <= 'bx;
    end
end

endmodule

